Encoding:

Format:

ADDU[_S].QB 

ADDU.QB   rd, rs, rt

ADDU_S.QB rd, rs, rt

Purpose:

Unsigned Add Quad Byte Vectors

Element-wise addition of two vectors of unsigned byte values to produce a vector of unsigned byte results, with optional saturation.

Description:

rd = sign_extend(sat8(rs31..24 + rt31..24)) || sat8(rs23..16 + rt23..16) || sat8(rs15..8 + rt15..8) || sat8(rs7..0 + rt7..0)

The four right-most byte elements in register rt are added to the corresponding byte elements in register rs.

For the non-saturating version of the instruction, the result modulo 256 is written into the corresponding element in register rd.

For the saturating version of the instruction, the addition is performed using unsigned saturating arithmetic. Results that overflow are clamped to the largest representable value (255 decimal, 0xFF hexadecimal) before being written to the destination register rd.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

For either instruction, if any of the individual additions result in overflow or saturation, a 1 is written to bit 20 in the

DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDU.QB:
   tempD7..0 = addU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = addU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = addU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = addU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)48 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
ADDU_S.QB:
   tempD7..0 = satAddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = satAddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = satAddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = satAddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)48 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function addU8( a7..0, b7..0 )
   temp8..0 = ( 0 || a7..0 ) + ( 0 || b7..0 )
   if ( temp8 = 1 ) then
      DSPControlouflag:20 = 1
   endif
   return temp7..0
endfunction addU8
function satAddU8( a7..0, b7..0 )
   temp8..0 = ( 0 || a7..0 ) + ( 0 || b7..0 )
   if ( temp8 = 1 ) then
      temp7..0 = 0xFF
      DSPControlouflag:20 = 1
   endif
   return temp7..0
endfunction satAddU8

Exceptions:

Reserved Instruction, DSP Disabled